This invention relates to integrated circuit devices, and more particularly to integrated circuit memory devices.
Integrated circuit memory devices are widely used in consumer and commercial applications. As the integration density of integrated circuit memory devices continues to increase, it may become increasingly important to improve the layout efficiency of the integrated circuit memory device. In particular, it may be increasingly important to improve the arrangement of functional blocks, also referred to herein as parts, of the integrated circuit device, relative to one another, on an integrated circuit substrate.
FIG. 1 is a circuit diagram of an integrated circuit memory device such as a conventional Dynamic Random Access Memory (DRAM). As shown in FIG. 1, an input/output (I/O) selecting part 30 is positioned between a pair of first and second sense amplifying parts 10, 20 for bit line pairs BL1, /BL1, and another input/output selecting part 30a is between another pair of first and second sense amplifying parts for BL2, /BL2.
A first transmission part 40 is arranged on the left side of the first sense amplifying part 10 of the bit line BL1, /BL1, BL2, /BL2 to control selection of the memory cell array part 60, and a first voltage equalizing part 50 is arranged on the left side of the first sense amplifying part 10 to control turning on/off of the first memory cell array part 60 of the bit line pairs BL1, /BL1, BL2, /BL2. Furthermore, a first memory cell array part is arranged on the left side of the first voltage equalizing part.
Likewise, a second transmission part 70 is arranged on the right side of the second sense amplifying part 20, and a first voltage equalizing part 80 is arranged on the right side of the second transmission part 70 to control turning on/off of each pair of bit lines BL1, /BL1, BL2, /BL2. Furthermore, a second memory cell array part 90 is arranged on the right side of the second voltage equalizing part 80.
In addition, the pairs of bit lines BL1, /BL1, BL2, /BL2 are respectively extended in the horizontal directions from the first memory cell array part 60 across the first transmission part 40 to the first sense amplifying part 10 and from the first sense amplifying part 10 across the second transmission part 70 to the second memory cell array part 90. Word lines (not shown) also vertically extend across the first and second memory cell arrays 60, 90. The first and second sense amplifying parts 10, 20 amplify by detecting a difference in voltage between pairs of bit lines associated with the memory cell array parts 60, 90. The input/output selection part 30 selectively outputs the voltage amplified by the first and second sense amplifying parts 10, 20 to the input/output lines IO1, IO2, /IO1, /IO2.
The operations of each of the parts that were described above are well known to those having skill in the art, and need not be described in detail herein. Moreover, it will be understood that all of the parts generally may be duplicated, in the vertical direction, for additional bit line pairs BL3, /BL3, BL4, /BL4 . . . , to form an integrated circuit memory device.
In the memory cell array parts 60, 90, memory cells (not shown) are arranged at the crossing points of the word lines (not shown) and bit lines. The voltage equalizing parts 50, 80 may be constructed with conventional circuits, and need not be described in detail.
In the transmission part 40, transistors Q4, Q5 are respectively connected to the bit lines BL1, /BL1, and signal PISOL is commonly transmitted to gates of the transistors Q4, Q5. Similarly, in the transmission part 70, transistors Q14, Q15 are respectively connected to the bit lines BL1, /BL1, and signal PISOR is commonly transmitted to gates of the transistors Q14, Q15.
In the sense amplifying part 10, the drain and gate of NMOS transistor Q6 are respectively connected to bit lines BL1, /BL1, and the drain and gate of NMOS transistor Q7 are respectively connected to bit lines BL1, /BL1. The sources S of the transistors Q6, Q7 are connected together. Likewise, in the sense amplifying part 20, the drain and gate of PMOS transistor Q16 are respectively connected to bit lines BL1, /BL1, and the drain and gate of PMOS transistor Q17 are respectively connected to bit lines BL1, /BL1. The sources S of the transistors Q16, Q17 are connected together. A predetermined power supply voltage Vss is supplied to the sources S of the transistors Q6, Q7 during the operations of the sense amplifying part 10, while another power supply voltage Vcc is supplied to the sources S of the transistors Q16, Q17 during the operations of the sense amplifying part 20.
In the input/output selection part 30, the drain D and source S of transistor Q8 are respectively connected to a bit line BL1 and an input/output line IO1, while the drain D and source S of transistor Q9 are respectively connected to bit line /BL1 and input/output line /IO1.
Similarly, in the input/output selection part 30a, the drain D and source S of transistor Q18 are respectively connected to a bit line BL2 and an input/output line IO2, while the drain D and source S of transistor Q19 are respectively connected to a bit line /BL2 and an input/output line /IO2. Signal IOG is commonly supplied to the gates of transistors Q8, Q9, Q18, Q19.
The layout view of the circuit thus constructed is shown in FIG. 2. As shown in FIG. 2, only the arrangement of the aforementioned parts relevant to the pairs of bit lines BL1, /BL1, BL2, /BL2 is described. It will be understood that parts relevant to all other pairs of bit lines BL3, /BL3, BL4, /BL4 . . . also may be arranged identical to those of the pairs of bit lines BL1, /BL1, BL2, /BL2. The detailed layout of the memory cell array parts 60, 90 also are not shown.
In FIG. 2, the regions filled with dots indicate an N+ active region 100 for NMOS transistors Q6, Q7 of a sense amplifying part 10, N+ active regions 311, 312 for NMOS transistors Q8, Q9 of an input/output selection part 30, N+ active regions 311, 312 for NMOS transistors Q18, Q19 of an input/output selection part 30a, N+ active regions 400, 700 for NMOS transistors Q4, Q5, Q14, Q15 of the transmission parts 40, 70, and N+ active regions 500, 800 for NMOS transistors Q1, Q2, Q3, Q11, Q12, Q13 of voltage equalizing parts 50, 80.
The P+ active region 200 for PMOS transistors Q16, Q17 of the sense amplifying part 20 and the P+ active regions 110, 210 for supplying substrate voltage VBB are designated by regions filled with triangular points.
The signal lines 510, 810, 410, 710 and gates 120, 130, 220, 230, 320, 330 to respectively transmit signals PEQL, PEQR, PISOL, PISOR may comprise polysilicon layers and designated by regions filled with slanted lines. The pairs of bit lines BL1, /BL1, BL2, /BL2 also may comprise polysilicon layers, being indicated by dotted lines. The input/output lines IO1, IO2, /IO1, /IO2 may be formed in metal layers, being designated by a solid line. The power lines 140, 240 of the sense amplifying parts 10, 20 may be formed in metal layers, being designated by a solid line.
The N+ and P+ active regions 100, 200 are positioned at both left and right sides of N+ active regions 311,312 for transistors Q8, Q9, Q18, Q19 of an input/output selection part 30. A P+ active region 200 is arranged in N well 201. The P+ active region 110 is vertically extended and arranged at the left side of the N+ active region 100. The P+ active region 210 is also vertically extended and arranged at the right side of the N well 201. The N+ active region 400 is horizontally extended and integrally connected from a predetermined right portion of the N+ active region 500. The N+ active region 700 is horizontally extended and integrally connected from a predetermined left portion of the N+ active region 500.
The signal line 510 is vertically extended along a channel area between the N+ active regions 500 for transistors Q1, Q2 of each pair of bit lines, and, in addition, horizontally extended along a channel area between the N+ active regions 500 for transistor Q3. Likewise, the signal line 810 is vertically extended along a channel region between the N+ active regions 800 for transistors Q11, Q12 of each pair of bit lines, and, in addition, horizontally extended along a channel area between the N+ active regions 800 for transistor Q13.
The signal line 410 is vertically extended along a channel area between the N+ active regions 400 for transistors Q4, Q5 of each pair of bit lines. Likewise, the signal line 710 is vertically extended along a channel region between the N+ active regions 700 for transistors Q14, Q15 of each pair of bit lines.
Gates 130, 120 are extended along a channel area between N+ regions 100 for the transistors Q7, Q6 of each pair of bit lines. The gates 230, 220 are also extended along a channel area between P+ active regions 200 for transistors Q17, Q16 of each pair of bit lines. A gate 320 is extended from the channel area of a N+ active region 311 toward that for transistor Q8. A gate 330 is extended from the channel area of a N+ active region 311 toward that for transistor Q18.
Each pair of bit lines BL1, /BL1, BL2, /BL2 is horizontally extended from the left side of the memory cell array part 60 across the signal line 510 to the N+ active region 500 for the drain of transistors Q1, Q2 and electrically connected by contacts C1, C2 with the N+ active region 500 for the drain of transistors Q1, Q2. Similarly, each pair of bit lines BL1, /BL1, BL2, /BL2 is also horizontally extended from the right side of the memory cell array part 90 across the signal line 810 to the N+ active region 800 for the drain D of transistors Q11, Q12 and electrically connected by contacts C11, C12 with the N+ active region 800 for the drain of transistors Q11, Q12.
Also, each pair of bit lines BL1, /BL1, BL2, /BL2 is horizontally extended from the N+ active region 400 for the source of transistors Q4, Q5 across N+ active regions 100, 311, 312 and P+ active regions 200, 210 to the N+ active region 700 for the source of transistors Q14, Q15. Accordingly, the pairs of bit lines BL1, /BL1, BL2, /BL2 are electrically connected by contacts C3, C4 to the source S of transistors Q4, Q5 and by contacts C13, 14 to the source S of transistors Q14, Q15.
Also, the pairs of bit lines BL1, /BL1, BL2, /BL2 are electrically connected by contacts C5, C6 to the drain D of Q6, Q7 and by contacts C7, C8 to the gates 130, 120 outside the N+ active region 100. Likewise, the pairs of bit lines BL1, /BL1, BL2, /BL2 are horizontally extended across a predetermined part of the relevant gates 220, 230 to the P+ active region 200 for the drain D of transistors Q16, Q17, and electrically connected by contacts C15, C16 to the drain D of transistors Q16, Q17. Furthermore, the pairs of bit lines BL1, /BL1, BL2, /BL2 are also electrically connected by contacts C17, C18 to the gates 230, 220 at a predetermined part of the P+ active region 200. The pairs of bit lines BL1, /BL1, BL2, /BL2 are electrically connected, respectively by contacts C9, C10 to the drain D of transistors Q8, Q9 and that of transistors Q18, Q19. Power line 140 is vertically extended across the pairs of bit lines BL1, /BL1, BL2, /BL2 and electrically connected by a contact C19 to the N+ active region 100 for the source S of transistors Q6, Q7. Similarly, a power line 240 is vertically extended across the pairs of bit lines BL1, /BL1, BL2, /BL2 and electrically connected by a contact C20 to the P+ active region 200 for the source S of transistors Q16, Q17.
The input/output lines IO1, IO2, /IO1, /IO2 are sequentially wired from the left to the right and vertically extended across the pairs of bit lines BL1, /BL1, BL2, /BL2.
In addition, the input/output line IO1 is vertically extended across the N+ active region 311 for the transistor Q8 of a pair of bit lines BL1, /BL1, and the input/output line /IO1 is vertically extended across the N+ active region 312 for the transistor Q9 of a pair of bit lines BL1, /BL1. Similarly, the input/output line IO2 is vertically extended across the N+ active region 311 for the transistor Q18 of a pair of bit lines BL2, /BL2, and the input/output line /IO2 is vertically extended across the N+ active region 312 for the transistor Q19 of a pair of bit lines BL2, /BL2. The input/output lines IO1, IO2 are electrically connected by contact C21, C23 to the source S of transistors Q8, Q18, and the input/output lines /IO1, IO2 are electrically connected by contact C22, C24 to the source S of transistors Q9, Q19. A line to supply signal IOG to a gate 320 is not shown.
Notwithstanding the arrangement of FIGS. 1 and 2, it may continue to be desirable to further increase the integration density of an integrated circuit memory device. Moreover, it also may be desirable to allow a reduction in the number of contacts that may be needed to interconnect the transistors of the integrated circuit memory device.
Embodiments of the present invention provide integrated circuit memory devices that include first and second memory cell arrays, first and second transmission parts between the first and second memory cell arrays, and first and second input/output selection parts between the first and second memory cell arrays, wherein the first transmission part is adjacent the first input/output selection part and wherein the second transmission part is adjacent the second input/output selection part. In other embodiments, a transistor in the first transmission part and a transistor in the first input/output selection part share a first common source/drain region. A transistor in the second transmission part and a transistor in the second input/output selection part share a second common source/drain region. Accordingly, the integration density may be increased, and the number of contacts may be decreased.
Other embodiments of the invention provide the first and second input/output selection parts between the first and second transmission parts. In other embodiments, at least one sense amplifier part is provided between the first and second input/output selection parts. The at least one sense amplifier may comprise first and second sense amplifier parts.
In yet other embodiments, a first equalizing part also may be provided between the first memory cell array and the first transmission part. A second equalizing part may be provided between the second memory cell array and the second transmission part. Finally, in still other embodiments, first input/output lines are connected to the first input/output selection part. Second input/output lines are connected to the second input/output part.